MT46V32M16CV-5B Datasheet, PDF(74/93 Page) Alliance Semiconductor Corporation

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MT46V32M16CV-5B Datasheet, PDF (74/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

◁

512Mb: x4, x8, x16 DDR SDRAM

Operations

Figure 38: Data Output Timing â tAC and tDQSCK

T01 T1

CK#

tLZ (MIN)

T2 T2n T3 T3n T4 T4n T5 T5n T6

tDQSCK2 (MAX)

tDQSCK2 (MIN)

tDQSCK2 (MAX) tHZ (MAX)

tDQSCK2 (MIN)

DQS or LDQS/UDQS3

tRPRE

tRPST

DQ (last data valid)

DQ (first data valid)

All DQ values collectively4

T2 T2n T3 T3n T4 T4n T5 T5n

T2n

T3n T4

T4n

T5 T5n

T2n T3

T3n T4

T4n T5 T5n

tLZ (MIN)

tAC5 (MIN)

tAC5 (MAX)

tHZ (MAX)

Notes:

1. READ command with CL = 2 issued at T0.

2. tDQSCK is the DQS output window relative to CK and is the âlong termâ component of the

DQS skew.

3. DQ transitioning after DQS transition define the tDQSQ window.

4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.

5. tAC is the DQ output window relative to CK and is the âlong termâ component of DQ skew.

6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.

7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.

WRITE

Note:

During a WRITE command, the value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the WRITE burst (after tWR time); if auto precharge is not

selected, the row will remain open for subsequent accesses.

Input data appearing on the DQ is written to the memory array subject to the DM input

logic level appearing coincident with the data. If a given DM signal is registered LOW, the

corresponding data will be written to memory. If the DM signal is registered HIGH, the

corresponding data inputs will be ignored, and a WRITE will not be executed to that

byte/column location.

For the WRITE commands used in the following illustrations, auto precharge is dis-

abled.

During WRITE bursts, the first valid data-in element will be registered on the first rising

edge of DQS following the WRITE command, and subsequent data elements will be

registered on successive edges of DQS. The LOW state on DQS between the WRITE

command and the first rising edge is known as the write preamble; the LOW state on

DQS following the last data-in element is known as the write postamble.

The time between the WRITE command and the first corresponding rising edge of DQS

(tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle).

All of the WRITE diagrams show the nominal case, and where the two extreme cases

(that is, tDQSS [MIN] and tDQSS [MAX]) might not be intuitive; they have also been

included. Figure 39 on page 76 shows the nominal case and the extremes of tDQSS for

BL = 4. Upon completion of a burst, assuming no other commands have been initiated,

the DQ will remain High-Z and any additional input data will be ignored.

PDF: 09005aef80768abb/Source: 09005aef82a95a3a

DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

▷