MT46V32M16CV-5B Datasheet, PDF (65/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 29: Consecutive READ Bursts
CK#
CK
Command
Address
DQS
T0
READ
Bank,
Col n
T1
NOP
CL = 2
DQ
CK#
CK
Command
Address
DQS
T0
READ
Bank,
Col n
T1
NOP
CL = 2.5
DQ
T2 T2n T3 T3n T4 T4n T5 T5n
READ
NOP
NOP
NOP
Bank,
Col b
DO
DO
n
b
T2 T2n T3 T3n T4 T4n T5 T5n
READ
NOP
NOP
NOP
Bank,
Col b
DO
DO
n
b
CK#
CK
Command
Address
T0
READ
Bank,
Col n
DQS
T1
T2
NOP
READ
Bank,
Col b
CL = 3
T3 T3n T4 T4n T5 T5n
NOP
NOP
NOP
DQ
DO
DO
n
b
Transitioning Data
Don’t Care
Notes:
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order follow-
ing DO b.
5. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
6. Example applies only when READ commands are issued to same device.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
65
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