MT46V32M16CV-5B Datasheet, PDF (6/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

512Mb: x4, x8, x16 DDR SDRAM
Functional Block Diagrams
Functional Block Diagrams
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory
containing 536,870,912 bits. It is internally configured as a 4-bank DRAM.
Figure 3: 128 Meg x 4 Functional Block Diagram
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
15
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
REFRESH ₁₃
COUNTER
ROW-
13
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
SENSE AMPLIFIERS
16384
2
BANK
CONTROL
LOGIC
2
COLUMN-
ADDRESS
11
12
COUNTER/
LATCH
1
I/O GATING
DM MASK LOGIC
8
2048
(x8)
COLUMN
DECODER
CK
4
8
READ
LATCH 4
MUX
COL0
MASK
WRITE
8
FIFO
2
&
DRIVERS
8
CK CK
Out In DATA
DATA
DLL
4
DQS
GENERATOR
DRVRS
1
INPUT
REGISTERS
1
1
1
1
4
4
4
4
DQS
1
RCVRS
4
CK
1
COL0
DQ0–DQ3
DQS
DM
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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