MT46V32M16CV-5B Datasheet, PDF (39/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
30. The input capacitance per pin group will not differ by more than this maximum
amount for any given device.
31. CK and CK# input slew rate must be t1 V/ns (t2 V/ns if measured differentially).
Figure 13: Derating Data Valid Window (^tQH – ^tDQSQ)
-6T @ ^tCK = 7.5ns
3.0ns
-75E / -75 @ ^tCK = 7.5ns
-6 @ ^tCK = 6ns
2.75
2.71
2.68
-6T @ ^tCK = 6ns
2.64
2.60
2.56
-5B @ ^tCK = 5ns
2.53
2.5ns
2.50
2.46
2.43
2.39
2.35
2.49
2.45
2.41
2.38
2.31
2.28
2.24
2.20
2.16
2.0ns
2.10
2.00
2.07
1.97
2.04
1.94
2.01
1.91
1.98
1.88
1.95
1.85
1.92
1.82
1.89
1.79
1.86
1.76
2.13
1.83
1.73
1.80
1.70
1.5ns
1.60
1.58
1.55
1.53
1.50
1.48
1.45
1.43
1.40
1.38
1.35
1.0ns
50/50
49/51
48/53
47/53
Clock Duty Cycle
46/54
45/55
32. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/
DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added
to ^tDS and ^tDH for each 100 mV/ns reduction in slew rate. For -5B, -6, and
-6T speed grades, the slew rate must be t0.5 V/ns. If the slew rate exceeds 4 V/ns,
functionality is uncertain.
33. V_DD must not vary more than 4% if CKE is not active while any bank is active.
34. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
the same amount.
35. ^tHP (MIN) is the lesser of ^tCL (MIN) and ^tCH (MIN) actually applied to the device CK
and CK# inputs, collectively, during bank active.
36. READs and WRITEs with auto precharge are not allowed to be issued until ^tRAS (MIN)
can be satisfied prior to the internal PRECHARGE command being issued.
37. Any positive glitch must be less than 1/3 of the clock cycle and not more than 400mV
or 2.9V (300mV or 2.9V maximum for -5B), whichever is less. Any negative glitch must
be less than 1/3 of the clock cycle and not exceed either –300mV or 2.2V (2.4V for -5B),
whichever is more positive. The average cannot be below the 2.5V (2.6V for -5B) mini-
mum.
38. Normal output drive curves:
38a. The full driver pull-down current variation from MIN to MAX process; tempera-
ture and voltage will lie within the outer bounding lines of the V-I curve of
Figure 14 on page 40.
38b. The driver pull-down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 14 on page 40.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
39
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