MT46V32M16CV-5B Datasheet, PDF (70/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 34: READ-to-PRECHARGE
CK#
CK
Command
Address
DQS
T0
READ
Bank a,
Col n
T1
NOP
CL = 2
T2 T2n T3 T3n T4
PRE
Bank a,
(a or all)
NOP
NOP
tRP
T5
ACT
Bank a,
Row
DQ
CK#
CK
Command
Address
T0
READ
Bank a,
Col n
DQS
DO
n
T1
T2 T2n T3 T3n T4
NOP
CL = 2.5
PRE
Bank a,
(a or all)
NOP
NOP
tRP
T5
ACT
Bank a,
Row
DQ
CK#
CK
Command
Address
T0
READ
Bank a,
Col n
DQS
DO
n
T1
T2
T3 T3n T4 T4n T5
NOP
PRE
Bank a,
(a or all)
CL = 3
NOP
NOP
tRP
ACT
Bank a,
Row
DQ
DO
n
Transitioning Data
Don’t Care
Notes:
1. Provided ^tRAS (MIN) is met, a READ command with auto precharge enabled would cause a
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
assumed that ^tRAS (MIN) is met.
7. An ACTIVE command to the same bank is only allowed if ^tRC (MIN) is met.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
70
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