MT46V32M16CV-5B Datasheet, PDF (59/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

512Mb: x4, x8, x16 DDR SDRAM
Operations
CAS Latency (CL)
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 25. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 37 on page 60 indi-
cates the operating frequencies at which each CL setting can be used.
Figure 25: CAS Latency
CK#
CK
Command
T0
READ
T1
NOP
T2
T2n
T3
T3n
NOP
NOP
DQS
CL = 2
DQ
CK#
CK
Command
T0
READ
DQS
DQ
T1
NOP
CL = 2.5
T2
T2n
T3
T3n
NOP
NOP
CK#
CK
Command
T0
READ
T1
NOP
T2
NOP
T3
T3n
NOP
DQS
CL = 3
Note:
DQ
Transitioning Data
Don’t Care
BL = 4 in the cases shown; shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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