MT46V32M16CV-5B Datasheet, PDF (46/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

512Mb: x4, x8, x16 DDR SDRAM
Commands
Table 32: Truth Table 3 – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table; Notes appear below
Current State
CS# RAS# CAS# WE# Command/Action
Notes
Any
Idle
Row active
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
H
X
X
X DESELECT (NOP/continue previous operation)
L
H
H
H NO OPERATION (NOP/continue previous operation)
L
L
H
H ACTIVE (select and activate row)
L
L
L
H AUTO REFRESH
7
L
L
L
L LOAD MODE REGISTER
7
L
H
L
H READ (select column and start READ burst)
10
L
H
L
L WRITE (select column and start WRITE burst)
10
L
L
H
L PRECHARGE (deactivate row in bank or banks)
8
L
H
L
H READ (select column and start new READ burst)
10
L
H
L
L WRITE (select column and start WRITE burst)
10, 12
L
L
H
L PRECHARGE (truncate READ burst, start PRECHARGE)
8
L
H
H
L BURST TERMINATE
9
L
H
L
H READ (select column and start READ burst)
10, 11
L
H
L
L WRITE (select column and start new WRITE burst)
10
L
L
H
L PRECHARGE (truncate WRITE burst, start
PRECHARGE)
8, 11
Notes:
1. This table applies when CKE_n-1 was HIGH and CKE_n is HIGH (see Table 35 on page 49) and
after ^tXSNR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (that is, the current state is for a specific
bank and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and ^tRP has been met.
• Row active: A row in the bank has been activated, and ^tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COM-
MAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 32 and according to Table 33 on
page 47.
• Precharging: Starts with registration of a PRECHARGE command and ends when ^tRP is
met. Once ^tRP is met, the bank will be in the idle state.
• Row activating: Starts with registration of an ACTIVE command and ends when ^tRCD is
met. Once ^tRCD is met, the bank will be in the “row active” state.
• Read with auto precharge enabled: Starts with registration of a READ command with
auto precharge enabled and ends when ^tRP has been met. Once ^tRP is met, the bank
will be in the idle state.
• Write with auto precharge enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when ^tRP has been met. Once ^tRP is met, the bank
will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.