MT46V32M16CV-5B Datasheet, PDF (16/93 Pages) Alliance Semiconductor Corporation – Double Data Rate (DDR) SDRAM

512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – I_DD
Table 7:
I_DD Specifications and Conditions (x16) Die Revision F Only
V_DDQ = 2.6V ±0.1V, V_DD = 2.6V ±0.1V (-5B); V_DDQ = 2.5V ±0.2V, V_DD = 2.5V ±0.2V (-6, -6T, -75E, -75Z, -75);
0°C d T_A d 70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 37–42; See also Table 10 on page 20
Parameter/Condition
Operating one-bank active-precharge current:
t_{RC =} t_{RC (MIN);} t_{CK =} t_{CK (MIN); DQ, DM, and DQS inputs}
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one-bank active-read-precharge current:
Burst = 4; ^tRC = ^tRC (MIN); ^tCK = ^tCK (MIN); I_OUT = 0mA;
Address and control inputs changing once per clock cycle
Precharge power-down standby current: All banks idle;
Power-down mode; ^tCK = ^tCK (MIN); CKE = (LOW)
Idle standby current: CS# = HIGH; All banks are idle;
t_{CK =} t_{CK (MIN); CKE = HIGH; Address and other control}
inputs changing once per clock cycle; V_IN = V_REF for DQ, DQS,
and DM
Active power-down standby current: One bank active;
Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW
Active standby current: CS# = HIGH; CKE = HIGH; One bank
active; ^tRC = ^tRAS (MAX); ^tCK = ^tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
Operating burst read current: Burst = 2; Continuous
burst reads; One bank active; Address and control inputs
changing once per clock cycle; ^tCK = ^tCK (MIN); I_OUT = 0mA
Operating burst write current: Burst = 2; Continuous burst
writes; One bank active; Address and control inputs changing
once per clock cycle; ^tCK = ^tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
Auto refresh burst current:
t_{RFC =} t_{RFC (MIN)}
t_{RFC = 7.8µs}
t_{RFC = 1.95µs}
Self refresh current: CKE d 0.2V
Standard
Low power (L)
Operating bank interleave read current: Four bank
interleaving READs (burst = 4) with auto precharge,
t_{RC = minimum} t_{RC allowed;} t_{CK =} t_{CK (MIN); Address and}
control inputs change only during active READ or WRITE
commands
Symbol -5B -6/6T -75E -75Z/-75
I_DD0 155 130 130 115
I_DD1 195 160 160 145
I_DD2P
5
5
5
5
I_DD2F 55 45 45
40
I_DD3P 45 35 35
30
I_DD3N 60 50 50
45
I_DD4R 210 165 165 145
I_DD4W 215 195 160 135
I_DD5 345 290 290 280
I_DD5A 11 10 10
10
I_DD5A 16 15 15
15
I_DD6
65
5
5
I_DD6A
4
3
3
3
I_DD7 480 405 400 350
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
23, 48
23, 48
24, 33
51
24, 33
23
23, 48
23
50
28, 50
28, 50
12
12
23, 49
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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