AS4C32M16SB-7TIN Datasheet, PDF (38/55 Pages) Alliance Semiconductor Corporation – 54pin TSOPII PACKAGE

AS4C32M16SB-6TIN
AS4C32M16SB-7TIN
AS4C32M16SB-7TCN
Figure 31.1. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
CLK
CKE
CS#
RAS#
CAS#
WE#
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
BA0,1
A10
RAx
A0-A9,
RAx
A11-A12
DQM
DQ
Hi-Z
Activate
Command
Bank A
CAx
CAy
CAz
Ax0 Ax1 Ax2 Ax3
Read
Command
Bank A
DAy0 DAy1
DAy3
Write
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latency
Read
Command
Bank A
Az0 Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Don’t Care
Confidential
- 38/55 -
Rev.1.0 June 2016