AS4C32M16SB-7TIN Datasheet, PDF (13/55 Pages) Alliance Semiconductor Corporation – 54pin TSOPII PACKAGE

AS4C32M16SB-6TIN
AS4C32M16SB-7TIN
AS4C32M16SB-7TCN
CLK
T0
T1 T2 T3 T4 T5 T6
T7
T8 T9
COMMAND
Bank A
Activate
NOP
NOP
WRITE A
Auto Precharge
NOP
NOP
tDAL
NOP
NOP
NOP
DQ
DIN A0
DIN A1
tDAL=tWR+tRP
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
Bank A
Activate
8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A12 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst Length
in the Mode register to make SDRAM useful for a variety of different applications. The default values of
the Mode Register after power-up are undefined; therefore this command must be issued at the
power-up sequence. The state of pins A0~ A12 in the same cycle is the data written to the mode
register. Two clock cycles are required to complete the write in the mode register (refer to the following
figure). The contents of the mode register can be changed using the same command and the clock
cycle requirements during operation as long as all banks are in the idle state.
Table 5. Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
RFU* 0
RFU*
WBL Test Mode CAS Latency BT Burst Length
A9 Write Burst Length A8 A7
Test Mode
0
Burst
00
Normal
1
Single Bit
1 0 Vendor Use Only
0 1 Vendor Use Only
A3 Burst Type
0 Sequential
1 Interleave
A6 A5 A4 CAS Latency
000
Reserved
001
Reserved
010
2 clocks
011
3 clocks
100
Reserved
All other Reserved
A2 A1 A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
1
1 Full Page (Sequential)
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
Confidential
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Rev.1.0 June 2016