AKD4691-A Datasheet, PDF (9/68 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4691

JP106
SDTO
[AKD4691-A]
SDTO1 SDTO2
* When a termination (51Ω) is not used, JP14 (EXT) should be open.
When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”.
(4-1-2) In case of supplying MCKI from X2 (11.2896MHz)
The jumper pins should be set as the following.
JP15
MCLK
JP19
PHASE
JP21
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
XTL DIR EXT
JP106
SDTO
THR INV
DIR 4040 DIR ADC
SDTO1 SDTO2
* When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”.
(4-2) Setting with PLL Slave Mode
BICK and LRCK are generated from MCKO of AK4691 on board divider. The generated BICK and LRCK is input
to the AK4691.
JP23 (M/S) should be set to “Slave”. In addition, the register of AK4691 should be set to “PLL Master Mode”
(Reference Clock: MCKI).
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP).
(4-2-1) In case of supplying MCLK from J11 (EXT)
The jumper pins should be set as the following.
JP14
EXT
JP15
MCLK
JP16
MKFS
JP17
BGFS
JP18
BICK_SEL
JP19
PHASE
XTL DIR EXT 256fs512fs1024fs MCKO ^32fs
JP21
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
JP108
MCKO
64fs
DIR
JP106
SDTO
4040
THR INV
DIR 4040 DIR ADC
SDTO1 SDTO2
*When a termination (51Ω) is not used, JP14 (EXT) should be open.
When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”.
<KM089100>
-9-
2007/06