AKD4691-A Datasheet, PDF (6/68 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4691

[AKD4691-A]
(3-2) Setting with PLL Slave Mode
A reference clock of PLL is selected among the input clocks supplied from PORT3 (DSP) to MCKI, BICK or
LRCK pin. The required clock to the AK4691 is generated by an internal PLL circuit.
JP23 (M/S) should be set to “Slave”.
(3-2-1) PLL Reference Clock: MCKI pin
The register of AK4691 should be set to “PLL Slave Mode” (Reference Clock: MCKI).
BICK and LRCK inputs should be synchronized with MCKO output. But the phase between MCKO and LRCK
dose not matter.
Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF
respectively on this board.
AK4691
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO1/2
SDTI
SDTI1/2
SDTO
Figure 3. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
The jumper pins should be set as the following.
JP15
MCLK
JP19
PHASE
JP21
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
XTL DIR EXT ^{THR INV}
JP106
SDTO
DIR 4040 DIR ADC
SDTO1 SDTO2
* When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”.
<KM089100>
-6-
2007/06