AKD4691-A Datasheet, PDF (8/68 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4691

[AKD4691-A]
(3-3) Setting with External Slave Mode
MCLK, BICK, LRCK, and SDTI are input from PORT3 (DSP).
JP23 (M/S) should be set to “Slave”. In addition, the register of AK4691 should be set to “EXT Slave Mode”.
AK4691
MCKO
MCKI
BICK
LRCK
256fs, 512fs or 1024fs
DSP or μP
MCLK
≥ 32fs
BCLK
1fs
LRCK
SDTO1/2
SDTI1/2
SDTI
SDTO


Figure 5. EXT Slave Mode
The jumper pins should be set as the following.
JP15
JP19
JP21
MCLK
PHASE
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
XTL DIR EXT ^{THR INV}
JP106
SDTO
DIR 4040 DIR ADC
SDTO1 SDTO2
* When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”.
(4) Evaluation of Loop-back.
(4-1) Setting with PLL Master Mode
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP).
JP23 (M/S) should be set to “Master”. In addition, the register of AK4691 should be set to “PLL Master Mode”.
(4-1-1) In case of supplying MCLK from J11 (EXT)
Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF
respectively on this board.
The jumper pins should be set as the following.
JP14
EXT
JP15
MCLK
JP19
PHASE
JP21
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
XTL DIR EXT ^{THR INV}
DIR 4040 DIR ADC
<KM089100>
-8-
2007/06