AKD4691-A Datasheet, PDF (11/68 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4691

[AKD4691-A]
(4-3-2) In case of using the clock divider on the board
ᶃ In case of supplying MCLK from J11 (EXT)
(e.g. MCLK=256fs, BICK=64fs)
The jumper pins should be set as the following.
JP14
EXT
JP15
MCLK
JP16
MKFS
JP17
BGFS
JP18
BICK_SEL
XTL DIR EXT 256fs512fs1024fs MCKO ^{32fs 64fs}
JP19
PHASE
JP21
LRCK_SEL
JP31
XTE
JP24
SDTI_SEL
DIR 4040
JP106
SDTO
THR INV DIR 4040
DIR ADC SDTO1 SDTO2
* When a termination (51Ω) is not used, JP14 (EXT) should be open.
When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”.
ᶄ In case of supplying MCKI from X2 (11.2896MHz)
The jumper pins should be set as the following.
JP15
MCLK
JP16
MKFS
JP17
BGFS
JP18
BICK_SEL
JP19
PHASE
XTL DIR EXT 256fs512fs1024fs MCKO ^32fs
JP21
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
64fs
DIR
JP106
SDTO
4040
THR INV
DIR 4040 DIR ADC
SDTO1 SDTO2
* When SDTO2 data is looped back to SDTI, JP106 should be set to “SDTO2”.
<KM089100>
- 11 -
2007/06