AKD4691-A Datasheet, PDF (5/68 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4691

[AKD4691-A]
(3) Evaluation of A/D, D/A using PORT3 (DSP).
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
(3-1) Setting with PLL Master Mode
The master clock is input from MCKI of PORT3 (DSP). An internal PLL circuit generates MCKO, BICK, and
LRCK.
JP23 (M/S) should be set to “Master”. In addition, the register of AK4691 should be set to “PLL Master Mode”.
SDTI, SDTO, LRCK and BICK of PORT3 are respectively connected with SDTO, SDTI, LRCK and BICK of DSP.
When MCKO is supplied to DSP, test pin (MCKO) should be directly connected to DSP.
Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF
respectively on this board.
AK4691
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO1/2
SDTI
SDTI1/2
SDTO
Figure 2. PLL Master Mode
The jumper pins should be set as the following.
JP15
MCLK
JP19
PHASE
JP21
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
XTL DIR EXT ^{THR INV}
JP106
SDTO
DIR 4040 DIR ADC
SDTO1 SDTO2
* When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”.
<KM089100>
-5-
2007/06