AKD4691-A Datasheet, PDF (7/68 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4691

[AKD4691-A]
(3-2-2) PLL Reference Clock: BICK or LRCK pin
The register of AK4691 should be set to “PLL Slave Mode” (Reference Clock = BICK or LRCK).
Loop-filter of PLL should be properly selected. Because resistor and capacitor values are 10kΩ and 4.7uF
respectively on this board.
AK4691
MCKO
MCKI
BICK
LRCK
SDTO1/2
SDTI
DSP or μP
32fs, 64fs
1fs
BCLK
LRCK
SDTI1/2
SDTO
Figure 4. PLL Slave Mode 2(PLL Reference Clock: BICK or LRCK pin)
The jumper pins should be set as the following.
JP14
EXT
JP15
MCLK
JP19
PHASE
JP21
LRCK_SEL
JP24
SDTI_SEL
JP31
XTE
XTL DIR EXT ^{THR INV}
JP106
SDTO
DIR 4040 DIR ADC
SDTO1 SDTO2
* When SDTO2 data is output to PORT3 (DSP), JP106 should be set to “SDTO2”.
<KM089100>
-7-
2007/06