AK4121A_10 Datasheet, PDF (9/20 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

[AK4121A]
OPERATION OVERVIEW
■ System Clock
The input port works in slave mode only. The output port works in slave and master mode. An internal system clock is
created by the internal PLL using ILRCK. The MCLK is not needed when the output port is in slave mode, and the
MCLK pin should be connected to DVSS. The CMODE2-0 pins must be controlled when PDN pin =“L”.
Mode
0
1
2
3
4
5
6
7
CMODE2
L
L
L
L
H
H
H
H
CMODE1
L
L
H
H
L
L
H
H
CMODE0
MCLK
L
256fso (fso~96kHz)
H
384fso (fso~96kHz)
L
512fso (fso~48kHz)
H
768fso (fso~48kHz)
L
Not used. Set to DVSS
H
-
L
-
H
Not used. Set to DVSS
Table 1. Master/Slave control
Master/Slave (Output Port)
Master
Master
Master
Master
Slave
(Reserved)
(Reserved)
Master (BYPASS mode)
■ Audio Interface Format
The IDIF2-0 pins select the data mode for the input port. The ODIF1-0 pins select the data mode for the output port. In
all modes the audio data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of OBICK.
Select these modes when PDN pin=“L”. In BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode
0
1
2
3
4
IDIF2
L
L
L
L
H
IDIF1
L
L
H
H
L
IDIF0
SDTI Format
L
16bit LSB Justified
H
20bit LSB Justified
L
20bit MSB Justified
H
20/16bit I²S Compatible
L
24bit LSB Justified
Table 2. Input Audio Data Formats
IBICK (Slave)
≥32fs
≥40fs
≥40fs
≥40fs or 32fs
≥48fs
Mode ODIF1 ODIF0
SDTO Format
OBICK (Slave)
0
L
L
16bit LSB Justified
64fs
1
L
H
20bit LSB Justified
64fs
2
H
L 20/16bit MSB Justified (Note 13) ≥40fs or 32fs
3
H
H 20/16bit I²S Compatible (Note 13) ≥40fs or 32fs
Note 13. The 16bit output is available only when the OBICK = 32fs.
Table 3. Output Audio Data Formats
OBICK (Master)
64fs
64fs
64fs
64fs
MS0337-E-06
-9-
2010/04