AK4121A_10 Datasheet, PDF (12/20 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

[AK4121A]
■ System Reset
Bringing the PDN pin=“L” places the AK4121A in the power-down mode and initializes the digital filter. This reset
should always be done after power-up. When the PDN pin = “L”, the SDTO output is “L”. Regarding the SDTO valid
time, please refer to the Table 5. Until the output data becomes valid, the SDTO pin outputs “L”.
Case 1
External clocks _{don’t care}
(input port)
SDTI
don’t care
External clocks
(output port)
don’t care
PDN
(state1)
(state1)
(state1)
(1)
(internal state) Power-down ^{PLL lock &}
fs detection
normal
operation
(state2)
(state2)
(state2)
don’t care
don’t care
don’t care
ta
tb
PD
PLL lock &
fs detection
normal
operation
Power-down
SDTO
“0” data
normal data
“0” data
normal data
“0” data
Case 2
External clocks
(input port)
SDTI
External clocks
(output port)
PDN
(no clock)
(don’t care)
(don’t care)
(internal state) Power-down
SDTO
“0” data
PLL
Unlock
(state1)
(state1)
(state1)
don’t care
don’t care
don’t care
(1)
PLL lock &
fs detection
normal
operation
Power-down
normal data
“0” data
Note:
(1) <100ms for recommended value 2, <200ms for recommended value 1. (Figure 11)
Figure 9. System Reset
Reset time
Data valid time
t_a
t_b
≤10ms
<100ms
10ms<
<200ms
Table 5. Reset time t_a and Data valid time t_b.
MS0337-E-06
- 12 -
2010/04