AK4121A_10 Datasheet, PDF (14/20 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

[AK4121A]
■ Grounding and Power Supply Decoupling
The AK4121A requires careful attention to power supply and grounding arrangements. VDD are usually supplied from
the system’s analog supply. AVSS and DVSS of the AK4121A must be connected to the analog ground plane.
System analog ground and digital ground should be connected together as close as possible to where the supplies are
brought onto the printed circuit board. Decoupling capacitors especially a 0.1μF ceramic capacitor for high frequency
noise should be placed as near to VDD as possible.
■ PLL Loop-Filter
The C1 (4.7μF) and R (560ohms) should be connected in series and attached between FILT pin and AVSS in parallel
with C2 (1.0nF). A Care should be taken to ensure that noise on the FILT pin is minimized.
AK4121A
FILT
R
C2
C1
AVSS
Parameter
Recommended value 1
Recommended value 2
R
560ohm +/−8%
1.2kohm +/−8%
C1
4.7μF +/−40%
2.2μF +/−40%
C2
1.0nF +/−40%
2.2nF +/−40%
FSI range
8k ~ 96kHz
16k ~ 96kHz
Note 14. Those recommended values include temperature dependence.
Figure 11. PLL Loop-Filter
MS0337-E-06
- 14 -
2010/04