AK4121A_10 Datasheet, PDF (6/20 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

[AK4121A]
SWITCHING CHARACTERISTICS
(Ta=−40∼85°C; VDD=3.0~3.6V; TVDD=3.0~5.5V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Input (MCLK)
Frequency
fCLK
8.192
-
Duty Cycle
dCLK
40
-
L/R clock for Input data (ILRCK)
Frequency
fs
8
Duty Cycle
Duty
48
50
L/R clock for Output data (OLRCK)
Frequency
(Note 8)
fs
32
Duty Cycle
Slave Mode
Duty
48
50
Master Mode
Duty
50
Audio Interface Timing
Input
IBICK Period
IBICK Pulse Width Low
IBICK Pulse Width High
ILRCK Edge to IBICK “↑”
(Note 9)
tBCK
tBCKL
tBCKH
1/64fs
65
65
ILRCK Frequency = 8kHz ~ 32kHz
ILRCK Frequency = 32kHz ~ 48kHz
ILRCK Frequency = 48kHz ~ 96kHz
BICK “↑” to ILRCK Edge
(Note 9)
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
tLRB
tLRB
tLRB
tBLR
tSDH
tSDS
1/256fs+45
1/256fs+25
1/256fs+15
30
30
30
Output (Slave Mode)
OBICK Period
OBICK Pulse Width Low
OBICK Pulse Width High
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
OLRCK to SDTO (MSB)
OBICK “↓” to SDTO
(Note 9)
(Note 9)
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/64fs
65
65
30
30
Output (Master Mode)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
fBCK
64fs
dBCK
50
tMBLR
−20
BICK “↓” to SDTO
tBSD
−20
Power-down & Reset Timing
PDN Pulse Width
(Note 10) tPD
150
Note 8. Min is 8kHz when BYPASS=“H”.
Note 9. BICK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK4121A must be reset by bringing PDN pin “H” to “L” upon power-up.
max Units
36.864 MHz
60
%
96
kHz
52
%
96
kHz
52
%
%
ns
ns
ns
16/256fs ns
16/256fs ns
16/256fs ns
ns
ns
ns
ns
ns
ns
ns
ns
30
ns
30
ns
Hz
%
20
ns
30
ns
ns
MS0337-E-06
-6-
2010/04