AK4121A_10 Datasheet, PDF (7/20 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

■ Timing Diagram
MCLK
LRCK
BICK
[AK4121A]
1/fCLK
tCLKH
tCLKL
1/fs
VIH
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
VIH
VIL
tBCK
VIH
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
LRCK
BICK
SDTO
SDTI
VIH
VIL
tBLR
tLRB
tLRS
tSDS
tSDH
VIH
VIL
tBSD
70%VDD
30%VDD
VIH
VIL
Figure 2. Audio Interface Timing at Slave Mode
MS0337-E-06
-7-
2010/04