AK4121A_10 Datasheet, PDF (13/20 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

[AK4121A]
■ Internal Reset Function for Clock Change
The AK4121A is reset automatically when the output clock is stopped. If the output clock is started again, normal data
is output within 100ms.
■ Sequence of changing clocks
The recommended sequence for changing clocks is shown in Figure 10.
External clocks
(Input port
or Output port)
PDN pin
Clocks 1
Don’t care
< 10msec
Clocks 2
< 100ms
(Internal state)
Normal operation Power-down
PLL lock &
fs detection
Normal operation
SDTO
Normal data
Note1
Note2
Normal data
SMUT E
(recommended)
0dB
Att.Level
-∞dB
1024/fso
1024/fso
Figure 10. Sequence of changing clocks
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before the PDN pin
changes to “L”, which will cause the data on SDTO to remain “0”.
Note 2. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” for 1024/fso+100ms or more
from the timing PDN pin changes to “H” while the SMUTE pin = “H”.
Note 3. When the PDN pin is not used for this clock change, a distorted signal may output for about 10ms ~ 100ms
(typ) after changing clocks.
MS0337-E-06
- 13 -
2010/04