AK4121A_10 Datasheet, PDF (16/20 Pages) Asahi Kasei Microsystems – Asynchronous Sample Rate Converter

[AK4121A]
SYSTEM DESIGN
Figure 13 and Figure 14 illustrate typical system connection diagrams. The evaluation board [AKD4121A]
demonstrates this application circuit, the optimum layout, and power supply arrangement and performance
measurement results.
4.7u ^{560 1.0n}
Control
fsi
DSP1
Mode setting
(fix to “H” or “L”)
+ ^10u
0.1u
FILT
AVSS
VDD
DVSS
PDN
TVDD
SMUTE
MCLK
DEM0 _AK4121A OLRCK
DEM1
OBICK
ILRCK
SDTO
IBICK
ODIF1
SDTI
ODIF0
IDIF0
IDIF1
CMODE2
CMODE1
IDIF2
CMODE0
+3.3V Analog
0.1u
+3.3~5V
Digital (*1)
fso
DSP2
Figure 13. Example of a typical design (Slave Mode)
4.7u ^{560 1.0n}
Control
fsi
DSP1
Mode setting
(fix to “H” or “L”)
+ ^10u
0.1u
FILT
AVSS
VDD
DVSS
PDN
TVDD
SMUTE
MCLK
DEM0 _AK4121A OLRCK
DEM1
OBICK
ILRCK
SDTO
IBICK
ODIF1
SDTI
ODIF0
IDIF0
IDIF1
CMODE2
CMODE1
IDIF2
CMODE0
+3.3V Analog
0.1u
256fso
+3.3~5V
Digital (*1)
fso
64fso
DSP2
Figure 14. Example of a typical design (Master Mode; MCLK=256fso)
*1. TVDD should be the same as the maximum input voltage.
MS0337-E-06
- 16 -
2010/04