AK4633 Datasheet, PDF (78/82 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4633]
„ Stop of Clock
Master clock can be stopped when ADC, DAC and programmable filter don’t operate.
1. PLL Master Mode
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
"H" or "L"
Input
(1)
(2)
(3)
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
(1) (2) Addr:01H, Data:08H
Stop an external MCKI
Figure 57. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (FCK or BICK pins)
PMPLL bit
(Addr:01H,D0)
External BICK
External FCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:04H
(2) Stop the external clocks
Figure 58. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and FCK clocks.
MS0447-E-03
- 78 -
2006/04