AK4633 Datasheet, PDF (28/82 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4633]
When PLL2 bit is “0”(PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2 bits
(Table 6).
Mode
0
1
2
Others
FS3 bit FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
Range
0
0
Don’t care Don’t care
7.35kHz ≤ fs ≤ 12kHz
0
1
Don’t care Don’t care 12kHz < fs ≤ 24kHz
1
0
Don’t care Don’t care 24kHz < fs ≤ 48kHz
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
Default
„ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, after PMPLL bit = “0” Æ “1” and until PLL locked , “L” are output from BICK and FCK pins and invalid
frequency clock is output from MCKO pin when MCKO bit is “1”. If MCKO bit is “0”, “L” is output from MCKO pin.
( Table 7)
In case that sampling frequency is changed, setting PMPLL bit to “0” once a time could be prevent BICK and FCK pins
output to “L” from unstable clocks.
PLL State
MCKO pin
MCKO bit = “0” MCKO bit = “1”
BICK pin
FCK pin
After that PMPLL bit “0” Æ “1” “L” Output
Invalid
Invalid
Invalid
PLL Unlock
“L” Output
Invalid
“L” Output
“L” Output
PLL Lock
“L” Output
256fs Output
See Table 9
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is changed.
After that, 256fs clock is output from MCKO pin while PLL is locked. However, the normal data couldn’t output from
ADC and DAC while PLL is unlocked. For DAC, the output signal should be muted by setting “0” to DACA and DACM
bits in Addr=02H.
PLL State
After that PMPLL bit “0” Æ “1”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
256fs Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MS0447-E-03
- 28 -
2006/04