AK4633 Datasheet, PDF (27/82 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4633]
„ Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4633 is power-down mode (PDN pin = “L”) and exits reset state, the AK4633 is slave mode. After exiting reset state,
the AK4633 goes master mode by changing M/S bit = “1”.
When the AK4633 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and
BICK pins of the AK4633 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating
state.
M/S bit
Mode
0
Slave Mode
Default
1
Master Mode
„ PLL Mode
Table 3. Select Master/Salve Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4633 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Setting of PLL Mode
PLL
R and C of VCOC PLL
PLL3 PLL2 PLL1 PLL0
Mode
bit bit bit bit
Reference
Clock Input
Pin
Input
Frequency
pin(Note 28)
R[Ω] C[F]
Lock
Time
(max)
0
0
0
0
0
FCK pin
1fs
6.8k 220n 160ms Default
1
0
0
0
1
BICK pin
16fs
10k
4.7n
2ms
2
0
0
1
0
BICK pin
32fs
10k
4.7n
2ms
3
0
0
1
1
BICK pin
64fs
10k
4.7n
2ms
4
0
1
0
0
MCKI pin 11.2896MHz 10k
4.7n 40ms
5
0
1
0
1
MCKI pin 12.288MHz
10k
4.7n 40ms
6
0
1
1
0
MCKI pin
12MHz
10k
4.7n 40ms
7
0
1
1
1
MCKI pin
24MHz
10k
4.7n 40ms
12
1
1
0
0
MCKI pin
13.5MHz
10k
10n 40ms
13
1
1
0
1
MCKI pin
27MHz
10k
10n 40ms
Others
Others
N/A
Note 28. The tolerance of R is ±5%, C is ±30%.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS2-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit Sampling Frequency
0
0
0
0
0
8kHz
Default
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”
MS0447-E-03
- 27 -
2006/04