AK4633 Datasheet, PDF (54/82 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4633]
„ Serial Control Interface
Internal registers may be written and read by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this
interface consists of a 2-bit Chip address (2bits, fixed to “10”), Read/Write, Register address (MSB first, 5bits) and
Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the
falling edge. It is available for writing the data on the rising edge of CSN. When reading operation, CDTI pin has become
an output mode at the falling edge of 8th CCLK and outputs D7-D0. The output finishes on the rising edge of CSN. The
CDTI pin is placed in a Hi-Z state except outputting data at read operation mode. The clock speed of CCLK is 5MHz
(max). The value of internal registers is initialized at PDN pin = “L”.
Note 33. It is available for reading the address 00H~0BH and 0DH~0FH. When reading the address 0CH and 10H ∼ 1FH,
the register values are invalid.
CSN
CCLK
CDTI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1” “0”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data
Figure 43. Serial Control I/F Timing
MS0447-E-03
- 54 -
2006/04