AK4633 Datasheet, PDF (6/82 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4633]
3. Register Setting
(1) When PLL reference clock is input from FCK or BICK pin, the setting of FS3-0 bits is changed as shown in the
following table.
Mode FS3 bit FS2 bit
FS1 bit
FS0 bit
0
0
0
Don’t care
1
0
1
Don’t care
2
1
0
Don’t care
Others
Others
ALL of modes are changed from AK4631.
Don’t care
Don’t care
Don’t care
Sampling Frequency
Range
7.35kHz ≤ fs ≤ 12kHz
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
N/A
(2) In EXT Slave Mode, the setting of FS3-0 bits is changed as shown in the following table.
.
Mode
FS3-2 bits
FS1 bit FS0 bit MCKI Input Sampling Frequency
Frequency
Range
0
Don’t care
0
0
256fs
7.35kHz ≤ fs ≤ 48kHz
1
Don’t care
0
1
1024fs
7.35kHz < fs ≤ 13kHz
2
Don’t care
1
0
512s
7.35kHz < fs ≤ 26kHz
3
Don’t care
1
1
256fs
7.35kHz ≤ fs ≤ 48kHz
Hatching parts are the setting changed from AK4631.
MS0447-E-03
-6-
2006/04