AK4633 Datasheet, PDF (49/82 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4633]
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC1 = ALC2 bits =“0” or PMPFIL bit = “0”.
• LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, IREF7-0/OREF7-0, ZELM, RFST1-0
Manual Mode
WR (ZTM1-0, WTM1-0)
WR (IREF7-0/OREF5-0)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +19.5dB
Limiter Detection Level = −4.1dBFS
ALC1 bit = “1”
WR (IVOL7-0/OVOL7-0)
*1
WR (RGAIN1, LMTH1,RFST1-0)
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0)
WR (ALC1= “1”)
*2
ALC Operation
(1) Addr=06H, Data=00H
(2) Addr=08H, Data=C5H
(3) Addr=09H, Data=C5H
(4) Addr=0BH, Data=28H
(5) Addr=07H, Data=21H
Note : WR : Write
*1: The value of volume at starting should be the same or smaller than REF’s.
*2: When setting ALC1 bit or ALC2 bit to “0”, the operation is shifted to manual mode after passing the zero crossing
time set by ZTM1-0 bits.
Figure 36. Registers set-up sequence at ALC operation
MS0447-E-03
- 49 -
2006/04