AK4122A Datasheet, PDF (50/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

[AK4122A]
1. Grounding and Power Supply Decoupling
The AK4122A requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS of the AK4122A must be
connected to analog ground plane. System analog ground and digital ground should be connected together near to where
the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4122A as
possible, with the small value ceramic capacitor being the nearest.
2. PLL Loop-Filter
The C1 (2.2μF) and R1 (470Ω) should be connected in series and attached between the FILT pin and AVSS in parallel with
C2 (2.2nF). Noises onto the FILT pin should be avoided.
AK4122A
FI LT
R1
C2
C1
AVSS
Parameter Recommended value
Accuracy
R1
470Ω
−5% ∼ +5%
C1
2.2μF
−50% ∼ +50%
C2
2.2nF
−50% ∼ +50%
Note: The accuracy includes temperature dependence.
Figure 30. Loop Filter for SRC
The R2 (12kΩ) should be connected in series between R pin and AVSS. Please be careful the noise onto the R pin.
AK4122A
R
R2
AVSS
Parameter Recommended value
Accuracy
R2
12kΩ
−5% ∼ +5%
Note: The accuracy includes temperature dependence.
Figure 31. Loop Filter for DIR
MS1076-E-01
- 50 -
2010/05