AK4122A Datasheet, PDF (28/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

[AK4122A]
■ Interrupt Handling for DIR
Following nine events cause that the INT2-0 pins go to “H”.
1. UNLCK: PLL unlock state detection
UNLCK bit =“1” when the PLL loses lock. The AK4122A loses synchronization when the interval of
two preambles is not correct or when those preambles are not correct.
2. PAR:
Parity error or biphase coding error detection
PAR bit =“1” when parity error or biphase coding error is detected. It is updated every sub-frame
cycle.
3. AUTO: Non-PCM or DTS-CD Bit Stream detection
The ORed result of NPCM and DTSCD bits is output to the AUTO bit.
4. V:
Validity flag detection
V bit =“1” when validity flag is detected. It is updated every sub-frame cycle.
5. AUDN: Non-audio detection
AUDN bit= “1” when the recovered channel status indicates “1”. It is updated every block cycle.
6. STC:
Sampling frequency or pre-emphasis information change detection
STC bit= “1” when FS3-0 or PEM bit is changed. Reading 07H register resets it.
7. CINT:
Channel status sync flag
CITN bit=“1” when received C bits differ from old ones, and stays “1” until this register is read.
Updated every block cycle. Reading 07H register resets it.
8. QINT:
U bit (Q-subcode) sync flag
QINT bit =“1” when the Q-subcode differs from old one, and stays “1” until this register is read.
Updated every sync code cycle for Q-subcode. Reading 07H register resets it.
9. DAT:
DAT Start ID detection
When the category code shows DAT, this bit becomes “1” if the Start ID of DAT is detected as “1”.
Reading 08H register resets it.
INT1-0 pins output an OR’ed signal based on the above nine interrupt events. When these registers are masked, the
interrupt event does not affect the operation of the INT1-0 pins (the masks do not affect the registers (UNLCK, PAR, etc.)
themselves). Once INT0 pin goes to “H”, it maintains “H” for 1024 cycles (this value can be changed by the EFH1-0 bits)
after all events which is not masked by mask bits are cleared. The INT1 pin immediately returns to “L” when those events
are cleared.
The INT2 pin outputs “H” by detecting a status change of events 1~5 and ORed results of the events 6~9. It stays “H”
until 07H and 08H registers are read. Mask bits are shared with INT0.
UNLCK, PAR, AUTO, V and AUDN bits indicate the interrupt status events above in real time. STC, QINT and CINT
bits at address 07H and DAT bit at 08H are changed to “1” by these events. Once STC, QINT or CINT and DAT bit goes
to “1”, it stays “1” until the register is read (07H, 08H (DAT bit)).
When the AK4122A loses lock, the channel status bits are initialized. In this initial state, the INT0 and INT2 pins output
an OR’ed signal between UNLCK and PAR bits. The INT1 pin outputs an OR’ed signal between AUTO, V and AUDN.
INT2-0 pins are “L” when the DIR is not selected.
When DIR is used as input port and the PLL loses lock (unlock state), the output data is muted automatically. When
AMUTE bit = “1”, SDTIO and SDTO are muted automatically when the AK4122A detects unlock, Non-Audio or
Non-PCM/DTS-CD. After the interrupt events are cleared, mute is cancelled automatically. When AMUTE bit = “0”,
SDTIO and SDTO outputs “L” when the PLL loses lock (unlock state), and outputs “H” when other errors (PAR, AUTO
and etc.) are occured.
MS1076-E-01
- 28 -
2010/05