AK4122A Datasheet, PDF (43/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

[AK4122A]
Addr Register Name
07H Receiver Status 0
R/W
Default
D7
D6
D5
D4
D3
D2
D1
UNLCK PAR
AUTO
V
AUDN
STC
CINT
RD
RD
RD
RD
RD
RD
RD
0
0
0
0
0
0
0
QINT: Q-subcode Buffer Interrupt
0: No change
1: Changed
This bit goes to “1” when Q-subcode stored in register addresses 13H to 1CH is updated.
CINT: Channel Status Buffer Interrupt
0: No change
1: Changed
This bit goes to “1” when C-bit stored in register addresses 0AH to 0EH changes.
STC:
Sampling Frequency or Pre-emphasis Information Change Detection
0: No detect
1: Detect
This bit goes to “1” when either the FS3-0 or PEM bit changes.
AUDN:
Audio Bit Output
0: Audio
1: Non audio
This bit is made by encoding channel status bits.
V: Validity Bit
0: Valid
1: Invalid
AUTO:
Non-PCM or DTS-CD Bit Steam Auto Detection
0: No detect
1: Detect
This bit outputs an OR’ed result of NPCM and DTSCD bits.
PAR:
Parity Error or Bi-phase Error Status
0: No error
1: Error
This bit goes to “1” if a parity error or biphase error is detected in the sub-frame.
UNLCK: PLL Lock Status
0: Lock
1: Unlock
QINT, CINT and STC bits are initialized when 07H is read.
D0
QINT
RD
0
MS1076-E-01
- 43 -
2010/05