AK4122A Datasheet, PDF (4/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

[AK4122A]
PIN/FUNCTION
No. Pin Name
I/O
Function
1 CDTI
I Control Data Input Pin
2 CDTO
O Control Data Output Pin
3 TST1
O Test 1 Pin
4 INT2
O Interrupt 2 Pin
5 TST2
O Test 2 Pin
6 TST3
Test 3 Pin
I
This pin should be connected to DVSS.
7 M/S2
Master / Slave Mode Pin for PORT2
I
“H” : Master mode, “L” : Slave Mode
8 M/S3
Master / Slave Mode Pin for PORT3
I
“H” : Master mode, “L” : Slave Mode
9 SMUTE
Soft Mute Pin
I
“H” : Soft Mute, “L” : Normal Operation
10 TST4
Test 4 Pin
I
This pin should be connected to AVSS.
11 TST5
Test 5 Pin
I
This pin should be connected to AVSS.
12 FILT
PLL Loop Filter Pin
O
470Ω±5% resistor and 2.2μF±50% ceramic capacitor in parallel with a
2.2nF±50% ceramic capacitor should be connected to AVSS externally.
13 AVSS
- Analog Ground Pin
14 AVDD
- Analog Power Supply Pin, 3.0 ∼ 3.6V
15 TST6
Test 6 Pin
I
This pin should be connected to AVSS.
16 RX1
I Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin)
17 TST7
Test 7 Pin
I
This pin should be connected to AVSS.
18 RX2
I Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
19 TST8
Test 8 Pin
I
This pin should be connected to AVSS.
20 RX3
I Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin)
21 TST9
Test 9 Pin
I
This pin should be connected to AVSS.
22 RX4
I Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
23 TST10
Test 10 Pin
I
This pin should be connected to AVSS.
24 TST11
O Test 11 Pin
Note: All input pins except internal biased pins should not be left floating.
MS1076-E-01
-4-
2010/05