AK4122A Datasheet, PDF (35/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

[AK4122A]
■ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The DIR of the AK4122A has a Non-PCM steam auto-detection function. In the 32-bit mode when Non-PCM preamble
based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM bit goes to “1”. The 96-bit sync code
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM bit to “1”.
Once the NPCM bit is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync
pattern being detected (Timing diagram: Figure 27and Figure 28). When those preambles are detected, the burst
preambles Pc and Pd (Pc: burst information, Pd: length code; Refer to Table 22, Table 23) that follow those sync codes are
stored to registers. The AK4122A also has a DTS-CD bitstream auto-detection function. When AK4122A detects
DTS-CD bitstream, the DTSCD bit goes to “1”. If the next sync code does not occur within 4096 frames, the DTSCD bit
returns to “0” until either the AK4122A detects the stream again. OR’ed value of the NPCM and DTSCD bits are output
to the AUTO bit. The AK4122A detects 14-bit sync word and 16-bit sync word of a DTS-CD bitstream, and these
detection can be ON/OFF by DTS14 and DTS16 bits.
■ Serial Control Interface
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes to high impedance after a low-to-high
transition of CSN. The maximum speed of CCLK is 5MHz. The chip address is fixed to “00”. Accessing to the chip
address except for “00” is invalid. The PDN pin = “L” resets the registers to their default values. Read/Write operation
can be made without MCLK, BICK and LRCK clocks.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
Write
CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTI
Read
CDTO
C1 C0 R/W A4 A3 A2 A1 A0
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0 ^Hi-Z
C1 - C0 : Chip Address (Fixed to "00")
R/W : READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 25. Control I/F Timing
MS1076-E-01
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2010/05