AK4122A Datasheet, PDF (25/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

[AK4122A]
■ 96kHz Clock Recovery
An integrated low jitter PLL of the DIR has a wide lock range of 32kHz to 96kHz and its lock time is less than 20ms. The
AK4122A has a sampling frequency detect function (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) that uses either clock
comparison against the MCLK2 or OMCLK frequency or the channel status information. The PLL loses synchronization
when receiving preambles in incorrect interval.
■ Biphase Input
Four inputs (RX1-4) are available for DIR. Each input includes an amplifier for unbalance loads that can accept 200mVpp
or greater signal. The IPS1-0 bits select the receiver channel (Table 14).
IPS1
IPS0
Input Data
0
0
RX1
(default)
0
1
RX2
1
0
RX3
1
1
RX4
Table 14. Recovery Data Select
■ Biphase Output
The AK4122A can output through data from the digital receiver inputs (RX1-4) to the TX pin. The OPS1-0 bits can select
the source of the TX pin output. TX output can be stopped by TXE bit. The AK4122A does not have a TX output buffer
(Line Driver), therefore the TX pin cannot drive the 75Ω coaxial cable directly.
OPS1
0
0
1
1
OPS0
Output Data
0
RX1
1
RX2
0
RX3
1
RX4
Table 15. Output Data Select for TX
(default)
MS1076-E-01
- 25 -
2010/05