AK4122A Datasheet, PDF (17/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

[AK4122A]
Note 14. In this case, PORT2 is input port. If PORT2 is unused, the digital I/O pins should be processed appropriately
as shown in Table 2.
M/S2 pin
L
H
Mode
Slave
Master
Unused pin Pin I/O
Setting
MCLK2
I
This pin should be connected to DVSS.
BICK2
I
This pin should be connected to DVSS.
LRCK2
I
This pin should be connected to DVSS.
SDTIO
I
This pin should be connected to DVSS.
MCLK2
I
This pin should be connected to DVSS.
BICK2
O This pin should be open.
LRCK2
O This pin should be open.
SDTIO
I
This pin should be connected to DVSS.
Table 2. Pin Setting for PORT2
Note 15. In this case, PORT3 is output port. If PORT3 is unused, the digital I/O pins should be processed appropriately
as shown in Table 3.
M/S3 pin
L
H
Mode
Slave
Master
Unused pin Pin I/O
Setting
OMCLK
I
This pin should be connected to DVSS.
BICK
I
This pin should be connected to DVSS.
LRCK
I
This pin should be connected to DVSS.
SDTO
O This pin should be open.
OMCLK
I
This pin should be connected to DVSS.
BICK
O This pin should be open.
LRCK
O This pin should be open.
SDTO
O This pin should be open.
Table 3. Pin Setting for PORT3
■ System Clock
PORT1 can be operated in slave mode only. PORT2 and PORT3 work in master mode and slave mode. Internal system
clock is created by internal PLL using LRCK1, LRCK2 or LRCK of DIR. The MCLK is not needed when PORT2 and
PORT3 are in slave mode. Set the MCLK2 pin and OMCLK pin to DVSS. When PORT2 and PORT3 are used in master
mode, the MCLK2 pin and OMCLK pin should be supplied MCLK. The M/S2 pin and M/S3 pin control master and slave
mode switching. Table 4 and Table 5 show setting of MCLK frequency when PORT2 and PORT3 are master mode. In
case of detecting the sampling frequency by MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of selected output
port (PORT2 or PORT3) should be input.
ICKS1
0
0
1
1
ICKS0
MCLK2
32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz
0
256fs
256fs
1
384fs
384fs
0
512fs
N/A
1
768fs
N/A
Table 4. MCLK2 frequency select for Master mode
(default)
OCKS1
0
0
1
1
OCKS0
OMCLK
32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz
0
256fs
256fs
1
384fs
384fs
0
512fs
N/A
1
768fs
N/A
Table 5. OMCLK frequency select for Master mode
(default)
MS1076-E-01
- 17 -
2010/05