AKD4673-A Datasheet, PDF (5/48 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in MIC/HP amplifier and TSC

[AKD4673-A]
(1-3) Evaluation of Loop-back using AK4114 <Default>
X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP).
The jumper pins should be set to the following.
JP15
MCLK
DIR
EXT
JP18
BICK_SEL
JP21
JP24
LRCK_SEL SDTI_SEL
JP19
JP22
PHASE ^4114_MCKI
DIR 4040 DIR 4040 DIR ADC THR INV
When AK4114 is used, JP16 (MKFS) and JP17 (BCFS) are not used. Therefore, JP16 (MKFS) should be set to
“256fs” and JP23 (BCFS) should be set to “64fs”.
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used.
(1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by
on-board divider.
J11 (EXT) is used. MCKI is supplied from J11 (EXT). BICK and LRCK are generated by 74HC4040 on
AKD4671-A. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP).
The jumper pins should be set as the following.
JP14
EXT
JP15
MCLK
DIR
EXT
JP18
BICK_SEL
JP21
JP24
LRCK_SEL SDTI_SEL
JP19
PHASE
DIR 4040 DIR 4040 DIR ADC THR INV
When a termination (51Ω) is unnecessary, please set JP14 (EXT) open.
JP16 (MKFS), JP17 (BCFS), and JP20 (LRCK) should be set according to the frequency of MCLK, BICK and
LRCK.
<KM086000>
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2007/5