AKD4673-A Datasheet, PDF (11/48 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in MIC/HP amplifier and TSC

[AKD4673-A]
(4) PLL Master Mode
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or
27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output
frequency is selected between 32fs or 64fs, by BCKO bit.
JP23 (M/S) should be set to “Master”. In addition, the register of AK4673 should be set to “PLL Master Mode”.
AK4673
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 7. PLL Master Mode
(4-1) Evaluation of Loop-back using AK4114
X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT3 (DSP) and J11 (EXT).
Using the AK4673’s internal PLL it is possible to evaluate various sampling frequencies.
The jumper pins should be set to the following.
JP15
MCLK
DIR
EXT
JP18
BICK_SEL
JP21
JP24
LRCK_SEL SDTI_SEL
JP19
PHASE
DIR 4040 DIR 4040 DIR ADC THR INV
(4-2) Evaluation of Loop-back that master clock is fed externally
J11 (EXT) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP). Exclude X’tal oscillator
from X1. Using the AK4673’s internal PLL it is possible to evaluate various sampling frequencies.
The jumper pins should be set to the following.
JP14
EXT
JP15
MCLK
DIR
EXT
JP18
BICK_SEL
JP21
JP24
LRCK_SEL SDTI_SEL
JP19
PHASE
DIR 4040 DIR 4040 DIR ADC THR INV
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