AKD4673-A Datasheet, PDF (14/48 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in MIC/HP amplifier and TSC

[AKD4673-A]
Other jumper pins set up
Main Board
[JP1] (GND): Analog ground and Digital ground
OPEN: Separated.
SHORT: Common. (The connector “DGND” can be open.) <Default>
[JP3] (HVDD_SEL): HVDD of the AK4673
OPEN: HVDD is supplied from “HVDD” jack.
SHORT: Supplied from the regulator (“HVDD” jack should be open). <Default>
[JP4] (AVDD_SEL): AVDD of the AK4673
OPEN: AVDD is supplied from “AVDD” jack.
SHORT: Supplied from the regulator (“AVDD” jack should be open). <Default>
[JP5] (DVDD_SEL): DVDD of the AK4673
OPEN: DVDD is supplied from “DVDD” jack.
SHORT: DVDD is supplied from “AVDD” (“DVDD” jack should be open). <Default>
[JP6] (TVDD_SEL): TVDD of the AK4673
OPEN: TVDD is supplied from “TVDD” jack.
SHORT: TVDD is supplied from “DVDD” (“TVDD” jack should be open). <Default>
[JP7] (VCC_SEL): VCC of the AK4673
OPEN: VCC is supplied from “VCC” jack.
SHORT: VCC is supplied from “TVDD” (“VCC” jack should be open). <Default>
[JP16] (MKFS): MCLK Frequency
256fs: 256fs. <Default>
512fs: 512fs.
1024fs: 1024fs.
384/768fs: 384fs
MCKO: MCKO is used.
[JP17] (BCFS): BICK Frequency
32fs: 32fs (When MCLK is 256fs or 512fs or 768fs or 1024fs.)
64fs:
64fs (When MCLK is 256fs or 512fs or 768fs or 1024fs.) <Default>
32fs-384: 32fs (When MCLK is 384fs.)
64fs-384: 64fs (When MCLK is 384fs.)
[JP22] (4114_MCKI): AK4114 Clock Source
OPEN: X’tal of AK4114 is used. <Default>
SHORT: X’tal of AK4114 is not used.
[JP25] (CTRL_SEL):Serial Control Interface (Must be set to I2C)
3-WIRE: Invalid
I2C:
I²C-bus Control Mode <Default>
Sub Board
[JP100] (I2CA_SEL): I2C (Must be set to H)
H:
Enable <Default>
L:
Unable
<KM086000>
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