AK4682 Datasheet, PDF (34/43 Pages) Asahi Kasei Microsystems – Multi-channel CODEC with 2Vrms Stereo Selector

[AK4682]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Powerdown 1
0
0 PWANA 0
0 SMAD SMDA RSTN
01H
Powerdown 2
0
0 PWDA PWAD 0
0
0
0
02H Audio Data Format
0
0 DIFB1 DIFB0 0 TDMA DIFA1 DIFA0
03H De-emphasis/ ATT speed DEM21 DEM20 DEM11 DEM10 DAC2 DAC1 ATSAD ATSDA
04H
Clock Control
0
ACKS DFS1 DFS0
0 CKSB1 CKSB0 MSB
05H Stereo Matrix Control PL23 PL22 PL21 PL20 PL13 PL12 PL11 PL10
06H Input Selector Control 1 AOUT13 AOUT12 AOUT11 AOUT10 AIN3 AIN2 AIN1 AIN0
07H Input Selector Control 2 AOUT33 AOUT32 AOUT31 AOUT30 AOUT23 AOUT22 AOUT21 AOUT20
08H ADC Lch Volume IATL7 IATL6 IATL5 IATL4 IATL3 IATL2 IATL1 IATL0
09H ADC Rch Volume IATR7 IATR6 IATR5 IATR4 IATR3 IATR2 IATR1 IATR0
0AH DAC1 Lch Volume OAT1L7 OAT1L6 OAT1L5 OAT1L4 OAT1L3 OAT1L2 OAT1L1 OAT1L0
0BH DAC1 Rch Volume OAT1R7 OAT1R6 OAT1R5 OAT1R4 OAT1R3 OAT1R2 OAT1R1 OAT1R0
0CH DAC2 Lch Volume OAT2L7 OAT2L6 OAT2L5 OAT2L4 OAT2L3 OAT2L2 OAT2L1 OAT2L0
0DH DAC2 Rch Volume OAT2R7 OAT2R6 OAT2R5 OAT2R4 OAT2R3 OAT2R2 OAT2R1 OAT2R0
Note: For addresses from 0EH to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset, but registers are not initialized to their default values.
Unused bits must contain a “0” data.
MS0610-E-01
- 34 -
2007/07