AK4682 Datasheet, PDF (15/43 Pages) Asahi Kasei Microsystems – Multi-channel CODEC with 2Vrms Stereo Selector

[AK4682]
LRCKB
fs
32.0kHz
44.1kHz
48.0kHz
128fs
-
-
-
■ DAC Clock Control
192fs
-
-
-
MCLKB (MHz)
256fs
384fs
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
512fs
16.3840
22.5792
24.5760
768fs
24.5760
33.8688
36.8640
Table 3. System clock example (ADC Slave Mode)
Sampling
Speed
Normal
External clocks (MCLKA, BICKA, LRCKA) must always be present whenever the DAC is in normal operation mode
(PDN pin = “H” and PWDA = “1”). The master clock (MCLKA) must be synchronized with LRCKA but the phase is
not critical. If these clocks are not provided, the DAC may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the DAC must be in the power-down mode (PDN pin =
“L” or PWDA = “0”) or in the reset mode (RSTN bit = “0”). After exiting reset at power-up etc., the DAC is in the
power-down mode until MCLKA and LRCKA are input.
There are two modes for controlling the sampling speed of DAC. One is the Manual Setting Mode (ACKS bit = “0”)
using the DFS1-0 bits, and the other is Auto Setting Mode (ACKS bit = “1”).
1. Manual Setting Mode (ACKS bit = “0”)
When the ACKS bit = “0”, DAC is in Manual Setting Mode and the sampling speed is selected by DFS1-0 bits (Table
4).
DFS1
0
0
1
1
DFS0
DAC Sampling Speed (fs)
0
Normal Speed Mode
32kHz~48kHz
1
Double Speed Mode
64kHz~96kHz
0
Quad Speed Mode
120kHz~192kHz
1
Not Available
-
(Note: ADC is always in Normal Speed Mode)
(default)
Table 4.DAC sampling speed (ACKS bit = “0”, Manual Setting Mode)
LRCKA
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLKA (MHz)
384fs
512fs
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
768fs
24.5760
33.8688
36.8640
BICKA (MHz)
64fs
2.0480
2.8224
3.0720
Table 5. DAC system clock example (DAC Normal Speed Mode @Manual Setting Mode)
LRCKA
fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLKA (MHz)
192fs
256fs
16.9344
22.5792
18.4320
24.5760
384fs
33.8688
36.8640
BICKA (MHz)
64fs
5.6448
6.1440
Table 6. DAC system clock example(DAC Double Speed Mode @Manual Setting Mode)
MS0610-E-01
- 15 -
2007/07