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AK4682 Datasheet, PDF (10/43 Pages) Asahi Kasei Microsystems – Multi-channel CODEC with 2Vrms Stereo Selector
[AK4682]
Parameter
Symbol
min typ
Audio Interface Timing (Slave Mode)
Normal mode(PORTA)
BICKA Period
tBCK
81
BICKA Pulse Width Low
tBCKL
32
Pulse Width High
LRCKA Edge to BICKA “↑” (Note: 13)
BICKA “↑” to LRCKA Edge (Note: 13)
tBCKH
32
tLRB
20
tBLR
20
SDTIA1-2 Hold Time
tSDH
10
SDTIA1-2 Setup Time
tSDS
10
Normal mode(PORTB)
BICKB Period
tBCK
324
BICKB Pulse Width Low
tBCKL
128
Pulse Width High
LRCKB Edge to BICKB “↑” (Note: 13)
BICKB “↑” to LRCKB Edge (Note: 13)
tBCKH
128
tLRB
80
tBLR
80
LRCKB to SDTOB (MSB)
BICKB “↓” to SDTOB
tLRS
tBSD
TDM 128 mode
BICKA Period
tBCK
81
BICKA Pulse Width Low
tBCKL
32
Pulse Width High
LRCKA Edge to BICKA “↑”
BICKA “↑” to LRCKA Edge
(Note: 13)
(Note: 13)
tBCKH
32
tLRB
20
tBLR
20
SDTIA1-2 Hold Time
tSDH
10
SDTIA1-2 Setup Time
tSDS
10
Audio Interface Timing (Master Mode)
Normal mode
BICKB Frequency
fBCK
64fs
BICKB Duty
BICKB “↓” to LRCKB Edge
BICKB “↓” to SDTO
Control Interface Timing (I2C Bus):
dBCK
tMBLR
tBSD
50
-40
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA 0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note: 14)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
-
Capacitive load on bus
Cb
0
Note: 13 BICK rising edge must not occur at the same time as LRCK edge.
Note: 14 Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 15 I2C is a registered trademark of Philips Semiconductors.
max Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
ns
80
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
40
ns
20
ns
400 kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
50
ns
400 pF
MS0610-E-01
- 10 -
2007/07