AK4682 Datasheet, PDF (16/43 Pages) Asahi Kasei Microsystems – Multi-channel CODEC with 2Vrms Stereo Selector

[AK4682]
LRCKA
Fs
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLKA (MHz)
192fs
256fs
33.8688
-
36.8640
-
384fs
-
-
BICKA (MHz)
64fs
11.2896
12.2880
Table 7. DAC system clock example (DAC Quad Speed Mode @Manual Setting Mode)
2. Auto Setting Mode (ACKS bit = “1”)
When the ACKS bit = “1”, DAC is in Auto Setting Mode and the sampling speed is selected automatically by the ratio
MCLKA/LRCKA as shown in the Table 8. and the internal master clock is set to the appropriate frequency (Table 9). In
this mode, the setting of DFS1-0 bits are ignored.
MCLKA
DAC Sampling Speed (fs) LRCKA
512fs, 768fs
Normal Speed Mode
32kHz~48kHz
256fs, 384fs
Double Speed Mode
64kHz~96kHz
128fs, 192fs
Quad Speed Mode
120kHz~192kHz
(Note: ADC is always in Normal Speed Mode)
Table 8. DAC Sampling Speed (ACKS bit = “1”, Auto Setting Mode)
LRCKA
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
-
-
-
-
22.5792
24.5760
192fs
-
-
-
-
-
33.8688
36.8640
MCLKA (MHz)
256fs
384fs
-
-
-
-
-
-
22.5792 33.8688
24.5760 36.8640
-
-
-
-
512fs
16.3840
22.5792
24.5760
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
Table 9. DAC System clock example (Auto Setting Mode)
Sampling
Speed
Normal
Double
Quad
■ DAC Audio Data Control
The DAC1, DAC2 bits select the output data for each DAC.
DAC1 bit
0
1
DAC1 Source
Normal Mode
TDMA bit = “0”
TDM Mode
TDMA bit = “1”
SDTIA1
L1, R1
SDTIA2
L2, R2
Table 10. DAC1 Source Control
DAC2 bit
0
1
DAC2 Source
Normal Mode
TDMA bit = “0”
TDM Mode
TDMA bit = “1”
SDTIA1
L1, R1
SDTIA2
L2, R2
Table 11. DAC2 Source Control
(default)
(default)
MS0610-E-01
- 16 -
2007/07