AK4682 Datasheet, PDF (29/43 Pages) Asahi Kasei Microsystems – Multi-channel CODEC with 2Vrms Stereo Selector

[AK4682]
■ Reset Function
When RSTN bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The DAC outputs
go to AVDD2 voltage and SDTOB pins go to “L”. Because some click noise occurs, the analog output should muted
externally if the click noise influences system application. The Figure 13 shows the power-up sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
Normal Operation
4~5/fs (8)
1~2/fs (8)
Digital Block Power-down
516/fs ⁽¹⁾
Init Cycle
Normal Operation
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
Normal Operation
Digital Block Power-down
GD ⁽²⁾
(3)
“0”data
Normal Operation
GD
(4)
DAC In
(Digital)
“0”data
(2)
GD
GD
DAC Out
(Analog)
(6) (5)
(6)
Clock In
MCLK,LRCK,SCLK
(7)
Don’t care
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) When RSTN bit = “0”, the analog outputs go to AVDD2 voltage.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLKA (MCLKB), BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode.
When exiting the reset mode, “1” should be written to RSTN bit after the external clocks (MCLKA (MCLKB),
BICKA (BICKB), LRCKA (LRCKB)) are fed.
(8) There is a delay about 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 13. Reset sequence example
MS0610-E-01
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2007/07