AK4682 Datasheet, PDF (32/43 Pages) Asahi Kasei Microsystems – Multi-channel CODEC with 2Vrms Stereo Selector

[AK4682]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4682.
After receipt of the start condition and the first byte, the AK4682 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4682. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 18. The Second Byte
After receipt of the second byte, the AK4682 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 19. Byte structure after the second byte
The AK4682 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4682 generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next
address automatically. If the address exceeds 0DH prior to generating the stop condition, the address counter will “roll
over” to 00H and the previous data will be overwritten.
S
T
A _Slave
R _Address
T
Register
Address(n)
Data(n)
Data(n+1)
S
T
Data(n+x) _O
P
SDA
S
P
A
A
A
A
C
C
C
C
K
K
K
K
Figure 20. WRITE Operation
MS0610-E-01
- 32 -
2007/07