AK4682 Datasheet, PDF (28/43 Pages) Asahi Kasei Microsystems – Multi-channel CODEC with 2Vrms Stereo Selector

[AK4682]
■ Power ON/OFF Sequence
The each block of the AK4682 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are
reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the
DAC outputs go to AVDD2 voltage and SDTOB pin goes to “L”. This reset must always be done after power-up.
In slave mode, after exiting reset at power-up etc., the DAC (ADC) starts to operate from the rising edge of LRCKA
(LRCKB) after MLCKA (MCLKB), and then the device is in the power-down mode until MCLKA (MCLKB) and
LRCKA (LRCKB) are input. In slave mode, the DAC (ADC) starts to operate by the input of MLCKA (MCLKB) after
exiting reset.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTOB
becomes available after 522/fs cycles of LRCKB clock. In case of the DAC, an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are AVDD2 voltage during the initialization. Figure 12 shows the
sequences of the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWAD and PWDA bits. These bits don’t initialize the
internal register values. When PWAD bit = “0”, the SDTOB pin goes to “L”. When PWDA bit = “0”, the DAC outputs
go to AVDD2 voltage. Since some click noise may occur, the analog output should muted externally if the click noise
influences system application.
Power
PDN
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
(1)
522/fs
Init Cycle
516/fs (2)
Init Cycle
Normal Operation
Power-down
Normal Operation
GD ⁽³⁾
Power-down
GD
ADC Out
“0”data (4)
(5)
(Digital)
“0”data
DAC In
(Digital)
“0”data
DAC Out
(6)
(Analog)
Clock In
Don’t care
MCLK,LRCK,SCLK
(3)
GD
(6)
“0”data
GD
(6)
(7)
Don’t care
External
Mute
(8)
Mute ON
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(6) Click noise occurs at the rising/falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLKA (MCLKB), BICKA (BICKB), and LRCKA (LRCKB)) are stopped, the AK4682
must be in the power-down mode.
(8) Please mute the analog output externally if the click noise (6) influences system application.
Figure 12. Power-down/up sequence example
MS0610-E-01
- 28 -
2007/07