AK4396 Datasheet, PDF (34/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of
AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. The power up
sequence between AVDD and DVDD is not critical. AVSS and DVSS must be connected to analog ground
plane. Decoupling capacitors for high frequency should be placed as near as possible.
2. Voltage Reference
The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to
AVDD and VREFL pin is normally connected to AVSS. VREFH and VREFL should be connected with a 0.1µF ceramic
capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor
attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted
coupling into the AK4396.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH − VREFL = 5V) centered around VCOM. The
differential outputs are summed externally, V_AOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−. If the
summing gain is 1, the output range is 5.6Vpp (typ, VREFH − VREFL = 5V). The bias voltage of the external summing
circuit is supplied externally. The input data format is 2's complement. The output voltage (V_AOUT) is a positive full scale
for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal V_AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 16 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 17 shows an example of differential outputs and LPF circuit example by three op-amps.
AK4396
AOUT-
AOUT+
2.4k
3.3n
2.4k
2.4k
2.4k
150
680p
+Vop
150
680p ^-Vop
Analog
Out
Figure 16. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)
Frequency Response
Gain
20kHz
−0.012dB
40kHz
−0.083dB
80kHz
−0.799dB
Table 15. Filter Response of External LPF Circuit Example 1 for PCM
MS0336-E-00
- 34 -
2004/08