AK4396 Datasheet, PDF (25/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
„ Power-Down
The AK4396 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 9 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK, BICK, LRCK
DZFL/DZFR
Normal Operation
Power-down
“0” data
GD (1)
(3) (2)
(4)
Don’t care
(6)
Normal Operation
GD (1)
(3)
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge (“↑ ↓”) of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN pin = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN pin = “L”).
Other:
After exiting power-down mode (PDN pin: “L” Æ “H”), AOUT pins go to VCOM voltage (VA/2). This time is set
by a capacitor connected to VCOM pin and the internal resistor of VCOM pin.
E.g. C = 10µF
1 τ (typ) = 10µF x 0.75kΩ = 7.5ms, 5τ (typ) = 37.5ms
1 τ (max) = 10µF x 0.975kΩ = 9.75ms, 5τ (max) = 48.75ms
Figure 9. Power-down/up sequence example
MS0336-E-00
- 25 -
2004/08