AK4396 Datasheet, PDF (26/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
„ Reset Function
When RSTN bit = “0”, the AK4396’s digital section is powered down but the internal register values are not initialized.
The analog outputs go to VCOM voltage and DZF pins of both channels go to “H”. Figure 10 shows the example of reset
by RSTN bit.
RSTN bit
Internal
RSTN Timing
3~4/fs (6)
2~3/fs (6)
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK, BICK, LRCK
DZFL/DZFR
Normal Operation
(1)
GD
Digital Block
Pd
“0” data
(3) (2)
Normal Operation
GD (1)
(3)
(4)
Don’t care
2/fs(5)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.
This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
Figure 10. Reset sequence example
MS0336-E-00
- 26 -
2004/08