AK4396 Datasheet, PDF (28/38 Pages) Asahi Kasei Microsystems – Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC

ASAHI KASEI
[AK4396]
„ Register Map
Addr
00H
01H
02H
03H
04H
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
D7
ACKS
DZFE
D/P
ATT7
ATT7
D6
0
DZFM
DSDM
ATT6
ATT6
D5
0
SLOW
DCKS
ATT5
ATT5
D4
0
DFS1
DCKB
ATT4
ATT4
D3
DIF2
DFS0
0
ATT3
ATT3
D2
DIF1
DEM1
DZFB
ATT2
ATT2
D1
DIF0
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the only internal timing is reset and the registers are not initialized to their default values.
When the state of P/S pin is changed, the AK4396 should be reset by PDN pin.
„ Register Definitions
Addr Register Name
00H Control 1
Default
D7
D6
D5
D4
D3
D2
D1
D0
ACKS
0
0
0
DIF2
DIF1
DIF0 RSTN
0
0
0
0
0
1
0
1
RSTN: Internal timing reset
0 : Reset. All registers are not initialized.
1 : Normal Operation (Default)
When the states of DFS1-0 bits change, the AK4396 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (see Table 11)
Initial value is “010” (Mode 2: 24bit MSB justified).
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0 : Disable : Manual setting mode (Default)
1 : Enable : Auto setting mode
When ACKS bit = “1”, MCLK frequency and the sampling frequency are detected automatically.
MS0336-E-00
- 28 -
2004/08